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19-1304; Rev 0; 10/97
Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs
_______________General Description
The MAX5152/MAX5153 low-power, serial, voltage-output, dual 13-bit digital-to-analog converters (DACs) consume only 500A from a single +5V (MAX5152) or +3V (MAX5153) supply. These devices feature Rail-toRail(R) output swing and are available in space-saving 16-pin QSOP and DIP packages. Access to the inverting input allows for specific gain configurations, remote sensing, and high output current capability, making these devices ideally suited for industrial process controls. These devices are also well suited for digitally programmable (4-20mA) current loops. The 3-wire serial interface is SPITM/QSPITM and MicrowireTM compatible. Each DAC has a doublebuffered input organized as an input register followed by a DAC register, which allows the input and DAC registers to be updated independently or simultaneously. Additional features include a programmable shutdown (2A), hardware-shutdown lockout, a separate voltage reference for each DAC, power-on reset, and an activelow clear input (CL) that resets all registers and DACs to zero. The MAX5152/MAX5153 provide a programmable logic output pin for added functionality, and a serial-data output pin for daisy chaining.
____________________________Features
o 13-Bit Dual DAC with Configurable Output Amplifier o Single-Supply Operation: +5V (MAX5152) +3V (MAX5153) o Rail-to-Rail Output Swing o Low Quiescent Current: 500A (normal operation) 2A (shutdown mode) o Power-On Reset Clears DAC Outputs to Zero o SPI/QSPI and Microwire Compatible o Space-Saving 16-Pin QSOP Package o Pin-Compatible 12-Bit Versions: MAX5156/MAX5157
MAX5152/MAX5153
______________Ordering Information
PART MAX5152ACPE MAX5152BCPE MAX5152ACEE MAX5152BCEE MAX5152BC/D TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP Dice* INL (LSB) 1/2 1 1/2 1 1
________________________Applications
Industrial Process Control Digital Offset and Gain Adjustment Remote Industrial Controls Motion Control Digitally Programmable 4-20mA Current Loops Automatic Test Equipment
Ordering Information continued at end of data sheet. *Dice are tested at TA = +25C, DC parameters only. Pin Configuration appears at end of data sheet.
_________________________________________________________Functional Diagram
DOUT CL PDL DGND AGND VDD REFA
DECODE CONTROL 16-BIT SHIFT REGISTER LOGIC OUTPUT SR CONTROL
INPUT REG A
DAC REG A
DAC A
OUTA
MAX5152 MAX5153
INPUT REG B DAC REG B DAC B
FBA
OUTB FBB
CS
DIN
SCLK UPO
REFB
Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5152/MAX5153
ABSOLUTE MAXIMUM RATINGS
VDD to AGND............................................................-0.3V to +6V VDD to DGND ...........................................................-0.3V to +6V AGND to DGND ..................................................................0.3V FBA, FBB to AGND.....................................-0.3V to (VDD + 0.3V) REF_, OUT_ to AGND.................................-0.3V to (VDD + 0.3V) Digital Inputs (SCLK, DIN, CS, CL, PDL) to DGND ................................................................-0.3V to +6V Digital Outputs (DOUT, UPO) to DGND .....-0.3V to (VDD + 0.3V) Maximum Current into Any Pin .........................................20mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 10.5mW/C above +70C) .............593mW QSOP (derate 8.30mW/C above +70C) .....................667mW CERDIP (derate 10.00mW/C above +70C) ................800mW Operating Temperature Ranges MAX5152_C_E/MAX5153_C_E ...........................0C to +70C MAX5152_E_E/MAX5153_E_E..........................-40C to +85C MAX5152_MJE/MAX5153_MJE ......................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX5152
(VDD = +5V 10%, VREFA = VREFB = 2.5V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, output buffer connected in unity-gain configuration (Figure 9).) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Tempco Gain Error Gain-Error Tempco VDD Power-Supply Rejection Ratio REFERENCE INPUT Reference Input Range Reference Input Resistance REF RREF Minimum with code 1555 hex Input code = 1FFF hex, VREF = 0.67Vp-p at 2.5VDC Input code = 0000 hex, VREF = (VDD - 1.4Vp-p) at 1kHz SINAD Input code = 1FFF hex, VREF = 1Vp-p at 2.5VDC, f = 25kHz CL, PDL, CS, DIN, SCLK CL, PDL, CS, DIN, SCLK 200 VIN = 0V to VDD 0.001 8 1 3.0 0.8 0 14 20 VDD 1.4 V k PSRR Normalized to 2.5V 4.5V VDD 5.5V N INL DNL VOS TCVOS (Note 1) Guaranteed monotonic Code = 20 Normalized to 2.5V 3 -0.5 3 20 200 6 MAX5152A MAX5152B 13 1/2 1 1 6 Bits LSB LSB mV ppm/C LSB ppm/C V/V SYMBOL CONDITIONS MIN TYP MAX UNITS
MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth Reference Feedthrough Signal-to-Noise plus Distortion Ratio DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance 2 VIH VIL VHYS IIN CIN V V mV A pF 600 -85 82 kHz dB dB
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs
ELECTRICAL CHARACTERISTICS--MAX5152 (continued)
(VDD = +5V 10%, VREFA = VREFB = 2.5V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, output buffer connected in unity-gain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN VDD 0.5 0.13 0.75 To 1/2LSB of full-scale, VSTEP = 2.5V Rail-to-rail (Note 2) IFB_ 20 0 to VDD 0 25 CS = VDD, fDIN = 100kHz, VSCLK = 5Vp-p 5 5 VDD IDD (Note 3) 4.5 0.5 2 5.5 0.65 10 1 0.1 0.40 TYP MAX UNITS DIGITAL OUTPUTS (DOUT, UPO) Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing Current into FBA or FBB Time Required to Exit Shutdown Digital Feedthrough Digital Crosstalk POWER SUPPLIES Positive Supply Voltage Power-Supply Current Power-Supply Current in Shutdown Reference Current in Shutdown TIMING CHARACTERISTICS SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time SCLK Rise to DOUT Valid Propagation Delay SCLK Fall to DOUT Valid Propagation Delay SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold CS Pulse Width High tCP tCH tCL tCSS tCHS tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 10 40 100 (Note 4) 100 40 40 40 0 40 0 80 80 ns ns ns ns ns ns ns ns ns ns ns ns V mA A A SR V/s s V A s nV-s nV-s VOH VOL ISOURCE = 2mA ISINK = 2mA V V
MAX5152/MAX5153
IDD(SHDN) (Note 3)
Note 1: Accuracy is specified from code 20 to code 8191. Note 2: Accuracy is better than 1LSB for VOUT greater than 6mV and less than VDD - 50mV. Guaranteed by PSRR test at the end points. . Note 3: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = Note 4: SCLK minimum clock period includes rise and fall times. _______________________________________________________________________________________ 3
Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5152/MAX5153
ELECTRICAL CHARACTERISTICS--MAX5153
(VDD = +2.7V to +3.6V, VREFA = VREFB = 1.25V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, output buffer connected in unity-gain configuration (Figure 9).) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Tempco Gain Error Gain-Error Tempco VDD Power-Supply Rejection Ratio REFERENCE INPUT (VREF) Reference Input Range Reference Input Resistance REF RREF Minimum with code 1555 hex Input code = 1FFF hex, VREF(AC) = 0.67Vp-p at 1.25VDC Input code = 0000 hex, VREF = (VDD - 1.4V) at 1kHz SINAD Input code = 1FFF hex, VREF = 1Vp-p at 1.25VDC, f = 15kHz CL, PDL, CS, DIN, SCLK CL, PDL, CS, DIN, SCLK 200 VIN = 0V to VDD 0 8 ISOURCE = 2mA ISINK = 2mA VDD - 0.5 0.13 0.4 0.1 2.2 0.8 0 14 VDD 1.4 V k PSRR Normalized to 1.25V 2.7V VDD 3.6V N INL DNL VOS TCVOS (Note 5) Guaranteed monotonic Code = 40 Normalized to 1.25V 6 -0.5 6 20 320 8 MAX5153A MAX5153B 13 1 2 1 6 Bits LSB LSB mV ppm/C LSB ppm/C V/V SYMBOL CONDITIONS MIN TYP MAX UNITS
MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth Reference Feedthrough Signal-to-Noise plus Distortion Ratio DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance Output High Voltage Output Low Voltage VIH VIL VHYS IIN CIN VOH VOL V V mV A pF V V 600 -92 73 kHz dB dB
DIGITAL OUTPUTS (DOUT, UPO)
4
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs
ELECTRICAL CHARACTERISTICS--MAX5153 (continued)
(VDD = +2.7V to +3.6V, VREFA = VREFB = 1.25V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, output buffer connected in unity-gain configuration (Figure 9).) PARAMETER DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing Current into FBA or FBB Time Required to Exit Shutdown Digital Feedthrough Digital Crosstalk POWER SUPPLIES Positive Supply Voltage Power-Supply Current Power-Supply Current in Shutdown Reference Current in Shutdown TIMING CHARACTERISTICS SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time SCLK Rise to DOUT Valid Propagation Delay SCLK Fall to DOUT Valid Propagation Delay SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold CS Pulse Width High tCP tCH tCL tCSS tCHS tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 10 40 100 (Note 4) 100 40 40 40 0 50 0 120 120 ns ns ns ns ns ns ns ns ns ns ns ns VDD IDD (Note 7) 2.7 0.5 1 3.6 0.6 8 1 V mA A A CS = VDD, fDIN = 100kHz, VSCLK = 3Vp-p IFB_ SR To 1/2LSB of full-scale, VSTEP = 1.25V Rail-to-rail (Note 6) 0.75 25 0 to VDD 0 25 5 5 0.1 V/s s V A s nV-s nV-s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5152/MAX5153
IDD(SHDN) (Note 7)
Note 4: SCLK minimum clock period includes rise and fall times. Note 5: Accuracy is specified from code 40 to code 8191. Note 6: Accuracy is better than 1LSB for VOUT greater than 6mV and less than VDD - 100mV. Guaranteed by PSRR test at the end points. . Note 7: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL =
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5
Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5152/MAX5153
__________________________________________Typical Operating Characteristics
(VDD = +5V, RL = 10k, CL = 100pF, FB_ tied to OUT_, TA = +25C, unless otherwise noted.)
MAX5152
REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
MAX5152 TOC01
SUPPLY CURRENT vs. TEMPERATURE
MAX5152 TOC02
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
VREF = 1Vp-p AT 2.5VDC CODE = 1FFF (HEX)
MAX5152 TOC03
0 -2 -4 RELATIVE OUTPUT (dB) -6 -8 -10 -12 -14 -16 -18 -20 0 600 1200 1800 2400 VREF = 0.67Vp-p AT 2.5VDC CODE = 1FFF (HEX)
0.60 RL = CODE = 1FFF (HEX) SUPPLY CURRENT (mA) 0.55
-30 -40 THD + NOISE (dB) -50 -60 -70 -80
0.50 CODE = 0000 (HEX) 0.45
0.40 3000 -60 -20 20 60 100 140 FREQUENCY (kHz) TEMPERATURE (C)
-90 0 10 FREQUENCY (kHz) 100
FULL-SCALE ERROR vs. LOAD
MAX5152 TOC04
REFERENCE FEEDTHROUGH AT 1kHz
-60 -70 RELATIVE OUTPUT (dB) -80 -90 -100 -110 -120 -130 -140 VREF = 3.6Vp-p AT 1.88VDC CODE = 0000 (HEX)
MAX5152-TOC05
POWER-DOWN CURRENT vs. TEMPERATURE
MAX5152 TOC06
0 VREF = 2.5V FULL-SCALE ERROR (LSB) -0.2
-50
3.0 2.5 2.0 1.5 1.0 0.5 0
-0.4
-0.6
-0.8
-1.0 0.1 1 10 LOAD (k) 100 1000
-150 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz)
POWER-DOWN CURRENT (A)
-55 -35 -15
5
25
45
65
85 105 125
TEMPERATURE (C)
OUTPUT FFT PLOT
MAX5152-TOC07
DYNAMIC-RESPONSE RISE TIME
MAX5152 TOC08
DYNAMIC-RESPONSE FALL TIME
MAX5152 TOC09
0 -10 -20 RELATIVE OUTPUT (dB) -30 -40 -50 -60 -70 -80 -90 -100 VREF = 3.6Vp-p AT 1.8VDC f = 1kHz CODE = 1FFF (HEX) NOTE: RELATIVE TO FULL SCALE
CS 5V/div AC COUPLED
CS 5V/div AC COUPLED
OUT_ 500mV/div
OUT_ 500mV/div
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz)
2s/div
2s/div
6
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs
____________________________Typical Operating Characteristics (continued)
(VDD = +3V, RL = 10k, CL = 100pF, FB_ tied to OUT_, TA = +25C, unless otherwise noted.)
MAX5152/MAX5153
MAX5153
REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
MAX5152 TOC10
SUPPLY CURRENT vs. TEMPERATURE
MAX5152 TOC11
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
VREF = 1Vp-p AT 1VDC CODE = 1FFF (HEX)
MAX5152 TOC12
0 -2 -4 RELATIVE OUTPUT (dB) -6 -8 -10 -12 -14 -16 -18 -20 0 500 1000 1500 2000 VREF = 0.67Vp-p AT 1.25VDC CODE = 1FFF (HEX)
0.60 RL = SUPPLY CURRENT (mA) 0.55
-30 -40 THD + NOISE (dB) -50 -60 -70 -80
CODE = 1FFF (HEX)
0.50
0.45
CODE = 0000 (HEX)
2500
0.40 -60 -20 20 60 100 140 TEMPERATURE (C)
-90 0 10 FREQUENCY (kHz) 100
FREQUENCY (kHz)
FULL-SCALE ERROR vs. LOAD
MAX5152 TOC13
REFERENCE FEEDTHROUGH AT 1kHz
MAX5152-TOC14
POWER-DOWN CURRENT vs. TEMPERATURE
MAX5251 TOC15
0 -0.2 FULL-SCALE ERROR (LSB) -0.4 -0.6 -0.8 -1.0 VREF = 1.25V -1.2 0.1 1 10 LOAD (k) 100
-50 -60 -70 RELATIVE OUTPUT (dB) -80 -90 -100 -110 -120 -130 -140 -150 VREF = 1.6Vp-p AT 0.88VDC CODE = 0000 (HEX)
3.0 2.5 2.0 1.5 1.0 0.5 0
1000
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz)
POWER-DOWN CURRENT (A)
-55 -35 -15
5
25
45
65
85 105 125
TEMPERATURE (C)
OUTPUT FFT PLOT
-10 -20 RELATIVE OUTPUT (dB) -30 -40 -50 -60 -70 -80 -90 -100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz) VREF = 1.6Vp-p AT 0.88VDC f = 1kHz CODE = 1FFF (HEX) NOTE: RELATIVE TO FULL SCALE
MAX5152-TOC16
0
DYNAMIC-RESPONSE RISE TIME
MAX5152 TOC17
DYNAMIC-RESPONSE FALL TIME
MAX5152 TOC18
CS 2V/div
CS 2V/div
OUT_ 500mV/div
OUT_ 500mV/div
2s/div
2s/div
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7
Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5152/MAX5153
____________________________Typical Operating Characteristics (continued)
(VDD = +5V (MAX5152), VDD = +3V (MAX5153), RL = 10k, CL = 100pF, FB_ tied to OUT_, TA = TMIN to TMAX, unless otherwise noted.)
MAX5152/MAX5153
MAX5152 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5152 TOC19
MAX5153 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5152 TOC19a
0.60 0.55 SUPPLY CURRENT (mA) 0.50 0.45 0.40 0.35 0.30 4.50 4.75 5.00 5.25 SUPPLY VOLTAGE (V) RL = CODE = 0000 (HEX) CODE = 1FFF (HEX)
0.55 CODE = 1FFF (HEX) 0.50 SUPPLY CURRENT (mA)
0.45 CODE = 0000 (HEX) 0.40
0.35 RL = 0.30 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
5.50
MAX5152 MAJOR-CARRY TRANSITION
MAX5152 TOC20
CS 2V/div
OUT_ 10mV/div AC COUPLED
2s/div
MAX5152 ANALOG CROSSTALK
MAX5152 TOC21
MAX5152 DIGITAL FEEDTHROUGH
MAX5152 TOC22
OUTA 1V/div
SCLK 5V/div OUTA 500V/div AC COUPLED
OUTB 200V/div AC COUPLED
200s/div
1s/div
8
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME AGND OUTA FBA REFA CL CS DIN SCLK DGND DOUT UPO PDL REFB FBB OUTB VDD Analog Ground DAC A Output Voltage DAC A Output Amplifier Feedback Input. Inverting input of the output amplifier. Reference for DAC A Active-Low Clear Input. Resets all registers to zero. DAC outputs go to 0V. Chip-Select Input Serial Data Input Serial Clock Input Digital Ground Serial Data Output User-Programmable Output Power-Down Lockout. The device cannot be powered down when PDL is low. Reference Input for DAC B DAC B Output Amplifier Feedback Input. Inverting input of the output amplifier. DAC B Output Voltage Positive Power Supply FUNCTION
MAX5152/MAX5153
_______________Detailed Description
The MAX5152/MAX5153 dual, 13-bit, voltage-output DACs are easily configured with a 3-wire serial interface. These devices include a 16-bit data-in/data-out shift register, and each DAC has a double-buffered input comprised of an input register and a DAC register (see Functional Diagram). Both DACs use an inverted R-2R ladder network that produces a weighted voltage proportional to the input voltage value. Each DAC has its own reference input to facilitate independent fullscale values. Figure 1 depicts a simplified circuit diagram of one of the two DACs.
FB_ R R R OUT_
2R
2R D0
2R D10
2R D11
2R D12
REF_ AGND SHOWN FOR ALL 1s ON DAC
Reference Inputs
The reference inputs accept both AC and DC values with a voltage range extending from 0V to (VDD - 1.4V). Determine the output voltage using the following equation: VOUT = VREF x NB / 8192 where NB is the numeric value of the DAC's binary input code (0 to 8191) and VREF is the reference voltage. The reference input impedance ranges from 14k (1555 hex) to several giga ohms (with an input code of 0000 hex). This reference input capacitance is code dependent and typically ranges from 15pF with an input code of all zeros to 50pF with an input code of all ones.
Figure 1. Simplified DAC Circuit Diagram
Output Amplifier
The output amplifier's inverting input is available to the user, allowing force and sense capability for remote sensing and specific gain configurations. The inverting input can be connected to the output to provide a unitygain buffered output. The output amplifiers have a typical slew rate of 0.75V/s and settle to 1/2LSB within 25s, with a load of 10k in parallel to 100pF. Loads less than 2k degrade performance.
9
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5152/MAX5153
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD A0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 C1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 C0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 D12................D0 MSB LSB 13 bits of DAC data 13 bits of DAC data 13 bits of DAC data 13 bits of DAC data 13 bits of DAC data xxxxxxxxxxxxx xxxxxxxxxxxxx 0 0 1 x xxxxxxxxx 1 0 1 x xxxxxxxxx 1 1 0 x xxxxxxxxx 1 1 1 x xxxxxxxxx 0 1 0 x xxxxxxxxx 0 1 1 x xxxxxxxxx 1 0 0 1 xxxxxxxxx 1 0 0 0 xxxxxxxxx 0 0 0 x xxxxxxxxx FUNCTION
Load input register A; DAC register is unchanged. Load input register B; DAC register is unchanged. Load input register A; all DAC registers are updated. Load input register B; all DAC registers are updated. Load all DAC registers from the shift register (start up both DACs with new data). Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers). Shut down both DACs if PDL = 1. Update DAC register A from input register A (start up DAC A with data previously stored in input register A). Update DAC register B from input register B (start up DAC B with data previously stored in input register B). Shut down DAC A when PDL = 1. Shut down DAC B when PDL = 1. UPO goes low (default). UPO goes high. Mode 1, DOUT clocked out on SCLK's rising edge. Mode 0, DOUT clocked out on SCLK's falling edge (default). No operation (NOP).
"x" = don't care Note: When A0, C1, and C0 = "0", D12, D11, D10, and D9 become control bits.
Power-Down Mode
The MAX5152/MAX5153 feature a software-programmable shutdown mode that reduces the typical supply current to 2A. The two DACs can be shut down independently or simultaneously by using the appropriate programming word. For instance, enter shutdown mode (for both DACs) by writing an input control word of 111XXXXXXXXXXXXX (Table 1). In shutdown mode, the reference inputs and amplifier outputs become high impedance, and the serial interface remains active. Data in the input registers is saved, allowing the MAX5152/MAX5153 to recall the output state prior to entering shutdown when returning to normal mode. Exit shutdown by recalling the previous condition or by updating the DAC with new information. When returning to normal operation (exiting shutdown), wait 20s for output stabilization.
10
Serial Interface
The MAX5152/MAX5153 3-wire serial interface is compatible with both Microwire (Figure 2) and SPI/QSPI (Figure 3) serial-interface standards. The 16-bit serial input word consists of an address bit, two control bits, and 13 bits of data (MSB to LSB) as shown in Figure 4. The address and control bits determines the response of the MAX5152/MAX5153, as outlined in Table 1. The MAX5152/MAX5153's digital inputs are double buffered, which allows any of the following: loading the input register(s) without updating the DAC register(s), updating the DAC register(s) from the input register(s), or updating the input and DAC registers concurrently. The address and control bits allow for the DACs to act independently.
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs
Send the 16-bit data as two 8-bit packets (SPI, Microwire) or one 16-bit word (QSPI), with CS low during this period. The address and control bits determine which register will be updated, as well as the state of the registers when exiting shutdown. The 3-bit address/control determines:
MICROWIRE PORT
MAX5152/MAX5153
SCLK
SK
MAX5152 MAX5153
DIN
SO
CS
I/O
Figure 2. Connections for Microwire
VCC
* registers to be updated * clock edge on which data is clocked out via the serial data output (DOUT) * state of the user-programmable logic output * configuration of the device after shutdown The general timing diagram in Figure 5 illustrates how data is acquired. Driving CS low enables the device to receive data. Otherwise, the interface control circuitry is disabled. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. As CS goes high, data is latched into the input and/or DAC registers depending on the address and control bits. The maximum clock frequency guaranteed for proper operation is 10MHz. Figure 6 depicts a more detailed timing diagram of the serial interface.
SS
DIN
MOSI SPI/QSPI PORT
MAX5152 MAX5153
SCLK
SCK
Serial Data Output (DOUT) DOUT is the internal shift register's output. It allows for daisy-chaining and data readback. The MAX5152/ MAX5153 can be programmed to shift data out of DOUT on SCLK's falling edge (Mode 0) or rising edge (Mode 1). Mode 0 provides a lag of 16 clock cycles, which maintains compatibility with SPI/QSPI and Microwire interfaces. In Mode 1, the output data lags 15.5 clock cycles. On power-up, the device defaults to Mode 0. User-Programmable Logic Output (UPO) UPO allows an external device to be controlled through the MAX5152/MAX5153 serial interface (Table 1), thereby reducing the number of microcontroller I/O pins required. On power-up, UPO is low. Power-Down Lockout Input (PDL) PDL disables software shutdown when low. When in shutdown, transitioning PDL from high to low wakes up the part with the output set to the state prior to shutdown. PDL can also be used to asynchronously wake up the device. Daisy Chaining Devices Any number of MAX5152/MAX5153s can be daisy chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain (Figure 7).
CS
I/O
CPOL = 0, CPHA = 0
Figure 3. Connections for SPI/QSPI
MSB ..................................................................................LSB 16 Bits of Serial Data Address Bits A0 Control Bits C1, C0 MSB.......Data Bits.........LSB D12.................................D0 13 Data Bits
1 Address/2 Control Bits
Figure 4. Serial-Data Format
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11
Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5152/MAX5153
CS COMMAND EXECUTED 1 DIN A0 C1 C0 D12 D11 D10 D9 8 D8 D7 9 D6 D5 D4 D3 D2 D1 16 D0
SCLK
Figure 5. Serial-Interface Timing Diagram
CS tCSO SCLK tDS DIN tDH tCSS tCL tCH tCP tCSH tCS1
tCSW
Figure 6. Detailed Serial-Interface Timing Diagram
SCLK
SCLK
SCLK
MAX5152 MAX5153
DIN CS DOUT DIN CS
MAX5152 MAX5153
DOUT DIN CS
MAX5152 MAX5153
DOUT
TO OTHER SERIAL DEVICES
Figure 7. Daisy Chaining MAX5152/MAX5153s
Since the MAX5152/MAX5153's DOUT has an internal active pull-up, the DOUT sink/source capability determines the time required to discharge/charge a capacitive load. Refer to the digital output V OH and V OL specifications in the Electrical Characteristics.
Figure 8 shows an alternative method of connecting several MAX5152/MAX5153s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC.
12
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5152/MAX5153
DIN SCLK CS1 CS2 CS3 TO OTHER SERIAL DEVICES
CS
CS
CS
MAX5152 MAX5153
SCLK DIN SCLK DIN
MAX5152 MAX5153
SCLK DIN
MAX5152 MAX5153
Figure 8. Multiple MAX5152/MAX5153s Sharing a Common DIN Line
Table 2. Unipolar Code Table (Gain = +1)
+5V/+3V REF_ VDD
DAC CONTENTS MSB LSB 11111 1111 1111
ANALOG OUTPUT
8191 +VREF 8192 4097 +VREF 8192 4096 VREF +VREF = 2 8192 4095 +VREF 8192 1 +VREF 8192
MAX5152 MAX5153
DAC
FB_
10000
OUT_
0000
0001
10000
AGND DGND
0000
0000
01111
1111
1111
Figure 9. Unipolar Output Circuit
00000 00000
0000 0000
0001 0000
0V
__________Applications Information
Unipolar Output
Figure 9 depicts the MAX5152/MAX5153 configured for unity-gain, unipolar operation. Table 2 lists the unipolar output codes. To increase dynamic range, specific gain configurations can be used as shown in Figure 10.
Bipolar Output
The MAX5152/MAX5153 can be configured for a bipolar output, as shown in Figure 11. The output voltage is given by the equation: VOUT = VREF [((2 x NB) / 8192) - 1] where NB represents the numeric value of the DAC's binary input code. Table 3 shows digital codes and the corresponding output voltage for Figure 11's circuit.
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5152/MAX5153
REF_ +5V/+3V VDD REF_ +5V/+3V 10k 10k
R2 FB_ R1
MAX5152 MAX5153
DAC
VDD
VOUT OUT_
MAX5152 MAX5153
DAC _
FB_
V+
VOUT OUT_ VDGND AGND
DGND
AGND
VOUT = 1 + R1 R2
( ) ( )( )
N VREF_ 8192
Figure 10. Configurable Output Gain
Figure 11. Bipolar Output Circuit
Table 3. Bipolar Code Table
DAC CONTENTS MSB LSB 11111 1111 1111 ANALOG OUTPUT
4095 +VREF 4096 1 +VREF 4096
+5V/ +3V +5V/+3V 26k AC REFERENCE INPUT
MAX495
10000 10000 01111
0000 0000 1111
0001 0000 1111
500mVp-p
10k REF_ VDD FB_
0V
1 -VREF 4096 4095 -VREF 4096 4096 -VREF = - VREF 4096
DGND
DAC_
OUT_
00000
0000
0001
MAX5152 MAX5153
AGND
00000
0000
0000
Figure 12. AC Reference Input Circuit
Using an AC Reference
In applications where the reference has an AC signal component, the MAX5152/MAX5153 have multiplying capabilities within the reference input voltage range specifications. Figure 12 shows a technique for applying a sinusoidal input to the reference input to REF_, where the AC signal is offset before being applied to the reference input.
14
Harmonic Distortion and Noise
The total harmonic distortion plus noise (THD+N) is typically less than -80dB at full scale with a 1Vp-p input swing at 5kHz. The typical -3dB frequency is 600kHz for both devices, as shown in the Typical Operating Characteristics.
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs
Digital Calibration and Threshold Selection
Figure 13 shows the MAX5152/MAX5153 in a digital calibration application. With a bright value applied to the photodiode (on), the DAC is digitally ramped up until it trips the comparator. The microprocessor stores this high calibration value. Repeat the process with a dim light (off) to obtain the dark current calibration. The microprocessor then programs the DAC to set an output voltage that is the midpoint of the two calibration values. Applications include tachometers, motion sensing, automatic readers, and liquid clarity analysis.
V+ REF_ +5V/+3V VDD PHOTODIODE
MAX5152/MAX5153
MAX5152 MAX5153
FB_
V+
Digital Control of Gain and Offset
The two DACs can be used to control the offset and gain for curve-fitting nonlinear functions, such as transducer linearization or analog compression/expansion applications. The input signal is used as the reference for the gain-adjust DAC, whose output is summed with the output from the offset-adjust DAC. The relative weight of each DAC output is adjusted by R1, R2, R3, and R4 (Figure 14).
OUT_ P DIN DGND AGND DAC _ R V-
VOUT
Figure 13. Digital Calibration
+5V/+3V VDD
MAX5152 MAX5153
VIN CS DIN SCLK CL VREF CONTROL/ SHIFT REGISTER REFA DACA
FBA R1 OUT_A R3 R4 FBB VOUT = GAIN - OFFSET R2 VOUT
DACB REFB
OUT_B
DGND
AGND
[ ][ ] = (V NA )( R2 )(1+ R4 ) (V [ 8192 R1+R2 R3 ] [
IN
REF
NB 8192
)( R4 )] R3
NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA. NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB.
Figure 14. Digital Control of Gain and Offset
______________________________________________________________________________________
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5152/MAX5153
Digital Programmable Current Source
Figure 15 depicts a digitally programmable, unidirectional current source that can be used in industrial control applications. The output current is: IOUT = (VREF / R) (NB / 8192) where NB is the DAC code and R is the sense resistor.
REF_ +5V/+3V VL VDD DAC_ OUT_ IOUT 2N3904
Power-Supply Considerations
On power-up, the input and DAC registers clear (reset to zero code). For rated performance, VREF_ should be at least 1.4V below VDD. Bypass the power supply with a 4.7F capacitor in parallel with a 0.1F capacitor to GND. Minimize lead lengths to reduce lead inductance.
MAX5152 MAX5153
DGND AGND
FB_
Grounding and Layout Considerations
Digital and AC transient signals on AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with an unbroken, lowinductance ground plane. Carefully lay out the traces between channels to reduce AC cross-coupling and crosstalk. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required.
R
Figure 15. Digitally Programmable Current Source
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs
_Ordering Information (continued)
PART MAX5152AEPE MAX5152BEPE MAX5152AEEE MAX5152BEEE MAX5152BMJE MAX5153ACPE MAX5153BCPE MAX5153ACEE MAX5153BCEE MAX5153BC/D MAX5153AEPE MAX5153BEPE MAX5153AEEE MAX5153BEEE MAX5153BMJE TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 CERDIP** 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP Dice* 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 CERDIP** INL (LSB) 1/2 1 1/2 1 1 1 2 1 2 2 1 2 1 2 2 DIP/QSOP
__________________Pin Configuration
TOP VIEW
AGND 1 OUTA 2 FBA 3 REFA 4 CL 5 CS 6 DIN 7 SCLK 8 16 VDD 15 OUTB 14 FBB
MAX5152/MAX5153
MAX5152 MAX5153
13 REFB 12 PDL 11 UPO 10 DOUT 9 DGND
*Dice are tested at TA = +25C, DC parameters only. **Contact factory for availability.
___________________Chip Information
TRANSISTOR COUNT: 3053 SUBSTRATE CONNECTED TO AGND
______________________________________________________________________________________
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5152/MAX5153
________________________________________________________Package Information
PDIPN.EPS
18
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs
___________________________________________Package Information (continued)
QSOP.EPS
MAX5152/MAX5153
______________________________________________________________________________________
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Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5152/MAX5153
___________________________________________Package Information (continued)
CDIPS.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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